ST7DALIF2 datasheet(88/171 Pages) STMICROELECTRONICS

88 / 171 page

Lite timer 2 (LT2)

ST7DALIF2

88/171

Bit 5 = TB Timebase period selection.

This bit is set and cleared by software.

0: Timebase period = tOSC * 8000 (1ms @ 8 MHz)

1: Timebase period = tOSC * 16000 (2ms @ 8 MHz)

Bit 4 = TB1IE Timebase Interrupt enable.

This bit is set and cleared by software.

0: Timebase (TB1) interrupt disabled

1: Timebase (TB1) interrupt enabled

Bit 3 = TB1F Timebase Interrupt Flag.

This bit is set by hardware and cleared by software reading the LTCSR register. Writing to

this bit has no effect.

0: No counter overflow

1: A counter overflow has occurred

Bits 2:0 = Reserved

15.6.5

Lite timer input capture register (LTICR)

Read only

Reset Value: 0000 0000 (00h)

Bits 7:0 = ICR[7:0] Input Capture Value

These bits are read by software and cleared by hardware after a reset. If the ICF bit in the

LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or falling

edge occurs on the LTIC pin.

ICR7

ICR6

ICR5

ICR4

ICR3

ICR2

ICR1

ICR0

Table 42.

Lite timer register map and reset values

Address

(Hex.)

label

76543210

LTCSR2

Reset

Value

000000

TB2IE

TB2F

LTARR

Reset

Value

AR7

AR6

AR5

AR4

AR3

AR2

AR1

AR0

LTCNTR

Reset

Value

CNT7

CNT6

CNT5

CNT4

CNT3

CNT2

CNT1

CNT0

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