ST7DALIF2 datasheet(34/171 Pages) STMICROELECTRONICS

34 / 171 page

Supply, reset and clock management

ST7DALIF2

34/171

Figure 11.

PLL output frequency timing diagram

When the PLL is started, after reset or wakeup from Halt mode or AWUFH mode, it outputs

the clock after a delay of tSTARTUP.

When the PLL output signal reaches the operating frequency, the LOCKED bit in the

SICSCR register is set. Full PLL accuracy (ACCPLL) is reached after a stabilization time of

tSTAB (see Figure 11 and Section 20.3.3: Internal RC oscillator and PLL on page 131)

Refer to Section 9.7.4 on page 44 for a description of the LOCKED bit in the SICSR register.

9.4

9.4.1

Main clock control/status register (MCCSR)

Read / Write

Reset Value: 0000 0000 (00h)

Bits 7:2 = Reserved, must be kept cleared.

Bit 1 = MCO Main Clock Out enable

This bit is read/write by software and cleared by hardware after a reset. This bit allows to

enable the MCO output clock.

0: MCO clock disabled, I/O port free for general purpose I/O.

1: MCO clock enabled.

Bit 0 = SMS Slow Mode select

This bit is read/write by software and cleared by hardware after a reset. This bit selects the

input clock fOSC2 or fOSC2/32.

0: Normal mode (fCPU = fOSC2

1: Slow mode (fCPU = fOSC2/32)

4/8 x

freq.

LOCKED bit set

tSTAB

tLOCK

input

tSTARTUP

00000

MCO

SMS

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