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ST7DALIF2 数据表(PDF) 29 Page - STMicroelectronics

部件名 ST7DALIF2
功能描述  Configurable watchdog timer
PDF  171 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7DALIF2 数据表(HTML) 29 Page - STMicroelectronics

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ST7DALIF2
Central processing unit (CPU)
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8.3.1
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations and to manipulate data.
8.3.2
Index registers (X and Y)
These 8-bit registers are used to create effective addresses or as temporary storage areas
for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to
indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures.
8.3.3
Program counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is
the LSB) and PCH (Program Counter High which is the MSB).
8.3.4
Condition code register (CC)
The 8-bit Condition Code register contains the interrupt masks and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions. These bits can be individually tested and/or controlled by specific
instructions.
CC
Reset value: 111x1xxx
76
543
21
0
11
I1
H
I0
N
Z
C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 6.
Arithmetic management bits
BIt Name
Function
4H
Half carry
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU
during an ADD or ADC instructions. It is reset by hardware during the same
instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.
2N
Negative
This bit is set and cleared by hardware. It is representative of the result sign of the last
arithmetic, logical or data manipulation. It is a copy of the result 7th bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative (that is, the most significant bit is a logic
1.
This bit is accessed by the JRMI and JRPL instructions.



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