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ST7DALIF2 数据表(PDF) 98 Page - STMicroelectronics |
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ST7DALIF2 数据表(HTML) 98 Page - STMicroelectronics |
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98 / 171 page ![]() DALI communication module ST7DALIF2 98/171 1: Acknowledge Bit 1 = RTS Receive/Transmit state. This bit is set/cleared by software and cleared by hardware after a reset. This bit must be set to ’1’ after a forward frame is received, if a backward frame is required. This bit must be cleared after a backward frame is transmitted, if a forward frame is required. 0: The DCM is set to Receive state 1: The DCM is set to Transmit state Bit 0 = FTS Force Transmit state. This bit is set/cleared by software and cleared by hardware after a reset. When this bit is set, the DCM is forced into Transmit state. Preferably before forcing the DCM into Transmit state, the user should reset and set the DCME bit in the DCMCR register. An interrupt flag (ITF) is generated after a forced transmission. 0: The DCM is not forced to Transmit state 1: The DCM is forced to Transmit state 16.11.6 DCM control/status register (DCMCSR) Read only (except for bit 7) Reset Value: 0000 0000 (00h) Bit 7 = ITE Interrupt Enable. This bit is set/cleared by software and cleared by hardware after a reset. When set, this bit allows the generation of DALI interrupts. 0: DCM interrupt (ITF) disabled 1: DCM interrupt (ITF) enabled Bit 6 = ITF Interrupt Flag. (Read only) This bit is set/cleared by hardware and read by software. This bit is set after the end of the "backward frame" transmission or the "forward frame" reception. It is cleared by setting the RTA bit in the DCMCR register. It is set after a forced transmission (see the FTS bit). 0: Not the end of reception/transmission 1: End of reception/transmission Bit 5 = EF Error Flag. (Read only) This bit is set/cleared by hardware. It is cleared by reading the DCMCSR register. This bit is set when either the DALI data format received is wrong or an interface failure is detected. 0: No data format error during reception 1: Data format error during reception Bit 4 = RTF Receive/Transmit Flag. (Read only) This bit is set/reset by hardware and read by software. 7 0 ITE ITF EF RTF CK3 CK2 CK1 CK0 |
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