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ST7DALIF2 数据表(PDF) 86 Page - STMicroelectronics

部件名 ST7DALIF2
功能描述  Configurable watchdog timer
PDF  171 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7DALIF2 数据表(HTML) 86 Page - STMicroelectronics

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Lite timer 2 (LT2)
ST7DALIF2
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15.4
Low power modes
15.5
Interrupts
Note:
The TBxF and ICF interrupt events are connected to separate interrupt vectors (see
Interrupts chapter).
They generate an interrupt if the enable bit is set in the LTCSR1 or LTCSR2 register and the
interrupt mask in the CC register is reset (RIM instruction).
15.6
Register description
15.6.1
Lite timer control/status register 2 (LTCSR2)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = TB2IE Timebase 2 Interrupt enable.
This bit is set and cleared by software.
0: Timebase (TB2) interrupt disabled
1: Timebase (TB2) interrupt enabled
Table 40.
Effect of low power modes on Lite timer
Mode
Description
Slow
No effect on Lite timer
(this peripheral is driven directly by fOSC2/32)
Wait
No effect on Lite timer
Active-halt
No effect on Lite timer
Halt
Lite timer stops counting
Table 41.
Interrupt control bits
Interrupt event
Event
flag
Enable
control
bit
Exit
from
Wait
Exit
from
Active-
halt
Exit
from
Halt
Timebase 1 Event
TB1F
TB1IE
Yes
Yes
No
Timebase 2 Event
TB2F
TB2IE
Yes
No
No
IC Event
ICF
ICIE
Yes
No
No
7
0
00
0000
TB2IE
TB2F



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