ST7DALIF2 datasheet(87/171 Pages) STMICROELECTRONICS

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ST7DALIF2

Lite timer 2 (LT2)

87/171

Bit 0 = TB2F Timebase 2 Interrupt Flag.

This bit is set by hardware and cleared by software reading the LTCSR register. Writing to

this bit has no effect.

0: No Counter 2 overflow

1: A Counter 2 overflow has occurred

15.6.2

Lite timer autoreload register (LTARR)

Read / Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = AR[7:0] Counter 2 Reload Value.

These bits register is read/write by software. The LTARR value is automatically loaded into

Counter 2 (LTCNTR) when an overflow occurs.

15.6.3

Lite timer counter 2 (LTCNTR)

Read only

Reset Value: 0000 0000 (00h)

Bits 7:0 = CNT[7:0] Counter 2 Reload Value.

This register is read by software. The LTARR value is automatically loaded into Counter 2

(LTCNTR) when an overflow occurs.

15.6.4

Lite timer control/status register (LTCSR1)

Read / Write

Reset Value: 0x00 0000 (x0h)

Bit 7 = ICIE Interrupt Enable.

This bit is set and cleared by software.

0: Input Capture (IC) interrupt disabled

1: Input Capture (IC) interrupt enabled

Bit 6 = ICF Input Capture Flag.

This bit is set by hardware and cleared by software by reading the LTICR register. Writing to

this bit does not change the bit value.

0: No input capture

1: An input capture has occurred

Note:

After an MCU reset, software must initialise the ICF bit by reading the LTICR register

AR7

AR3

AR2

AR1

AR0

CNT7

CNT3

CNT2

CNT1

CNT0

ICIE

ICF

TB1IE

TB1F

ST7DALIF2 数据表(PDF) 87 Page - STMicroelectronics

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