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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7DALIF2 数据表(PDF) 71 Page - STMicroelectronics |
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ST7DALIF2 数据表(HTML) 71 Page - STMicroelectronics |
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71 / 171 page  ST7DALIF2 Watchdog timer (WDG) 71/171 13.6 Register description 13.6.1 Control register (CR) Read/Write Reset Value: 0111 1111 (7Fh) Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. Bits 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared). 7 0 WDGA T6 T5 T4 T3 T2 T1 T0 Table 35. Watchdog timer register map and reset values Address (Hex.) Register label 76543210 002Eh WDGCR Reset Value WDGA 0 T6 1 T5 1 T4 1 T3 1 T2 1 T1 1 T0 1 |
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