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ST7DALIF2 数据表(PDF) 73 Page - STMicroelectronics |
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ST7DALIF2 数据表(HTML) 73 Page - STMicroelectronics |
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73 / 171 page  ST7DALIF2 12-bit autoreload timer 2 (AT2) 73/171 Figure 33. Block diagram 14.3 Functional description 14.3.1 PWM mode This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output pins. The PWMx output signals can be enabled or disabled using the OEx bits in the PWMCR register. PWM frequency and duty cycle The four PWM signals have the same frequency (fPWM) which is controlled by the counter period and the ATR register value. fPWM = fCOUNTER / (4096 - ATR) Following the above formula, ● If fCOUNTER is 32 MHz, the maximum value of fPWM is 8 MHz (ATR register value = 4092), the minimum value is 8 kHz (ATR register value = 0) ● If fCOUNTER is 4 Mhz, the maximum value of fPWM is 2 MHz (ATR register value = 4094),the minimum value is 1 KHz (ATR register value = 0). Note: The maximum value of ATR is 4094 because it must be lower than the DCR value which must be 4095 in this case. At reset, the counter starts counting from 0. When a upcounter overflow occurs (OVF event), the preloaded Duty cycle values are transferred to the Duty Cycle registers and the PWMx signals are set to a high level. When ATCSR CMPIE OVFIE OVF CK0 CK1 ICIE ICF 0 12-BIT AUTORELOAD REGISTER 12-BIT UPCOUNTER CMPF2 CMPF1 CMPF3 CMPF0 CMP REQUEST OVF INTERRUPT REQUEST fCPU ATIC 12-BIT INPUT CAPTURE REGISTER IC INTERRUPT REQUEST ATR ATICR fCOUNTER CNTR 32 MHz (1 ms fLTIMER @ 8MHz) CMPFx bit POL- ARITY OPx bit PWMx COMP- PARE fPWM OEx bit 4 PWM Channels INTERRUPT timebase DCR0H DCR0L Preload Preload on OVF Event 12-BIT DUTY CYCLE VALUE (shadow) IF TRAN=1 |
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