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ST7DALIF2 数据表(PDF) 91 Page - STMicroelectronics

部件名 ST7DALIF2
功能描述  Configurable watchdog timer
PDF  171 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7DALIF2 数据表(HTML) 91 Page - STMicroelectronics

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DALI communication module
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16.3
DALI standard protocol
The DALI protocol uses the bi-phase Manchester asynchronous serial data format. All the
bits of the frame are bi-phase encoded except the two stop bits.
The transmission rate is about 1.2 kHz. The bi-phase bit period is 833.33 us ±10%.
A forward frame consists of 19 bi-phase encoded bits:
– 1 start bit (0->1: logical ’1’)
– 1 address byte (8-bit address)
– 1 data byte (8-bit data)
– 2 high level stop bits (no change of phase)
A backward frame consists of 11 bi-phase encoded bits:
– 1 start bit (0->1: logical ’1’)
– 1 data byte (8-bit data)
– 2 high level stop bits (no change of phase)
A forward frame consists of 19 bi-phase encoded bits: 1 start bit (logical ’1’), 1 address byte
and 1 data byte. The frame is terminated by 2 stop bits (idle). The stop bits do not contain
any change of phase.
A backward frame consists of 11 bi-phase encoded bits: 1 start bit (logical ’1’) and 1 data
byte. The frame is terminated by 2 stop bits (idle). The stop bits do not contain any change
of phase.
The transmission rate, expressed as a bandwidth, is specified at 1.2 kHz for the forward
channel and for the backward channel.
The settling time between two subsequent forward frames is 9.17 ms (minimum).
The settling time between forward and backward frames is between 2.92 ms and 9.17 ms. If
a backward frame has not been started after 9.17 ms, this is interpreted as "no answer".
In the event of code violation, the frame is ignored. After a code violation has occurred, the
system is ready again for data reception.
Figure 42.
DALI standard frame
a7
d7
a6
a5
a4
a3
a2
a1
a0
d6
d5
d4
d3
d2
d1
d0
2T
2T
2T
2T
2T
2T
2T
2T
2T
2T
2T
2T
2T
2T
2T
2T
2T
4T
stop bits
start bit
address byte
data byte
FORWARD FRAME
d7
d6
d5
d4
d3
d2
d1
d0
2T
2T
2T
2T
2T
2T
2T
2T
2T
start bit
data byte
BACKWARD FRAME
stop bits
4T
BI-PHASE LEVELS
Logical ’1’
Logical ’0’
2T
2T
2T = 833.33 us ±10%



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