ST7DALIF2 datasheet(27/171 Pages) STMICROELECTRONICS

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ST7DALIF2

Data EEPROM

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7.7

7.8

EEPROM control/status register (EECSR)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:2 = Reserved, forced by hardware to 0.

Bit 1 = E2LAT Latch Access Transfer

This bit is set by software. It is cleared by hardware at the end of the programming cycle. It

can only be cleared by software if the E2PGM bit is cleared.

0: Read mode

1: Write mode

Bit 0 = E2PGM Programming control and status

This bit is set by software to begin the programming cycle. At the end of the programming

cycle, this bit is cleared by hardware.

0: Programming finished or not yet started

1: Programming cycle is in progress

Note:

If the E2PGM bit is cleared during the programming cycle, the memory data is not

guaranteed

000000

E2LAT

E2PGM

Table 5.

Data EEPROM register map and reset values

Address

(Hex.)

label

7654

3210

0030h

EECSR

Reset

Value

0000

E2LAT

E2PGM

ST7DALIF2 数据表(PDF) 27 Page - STMicroelectronics

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