ST7DALIF2 datasheet(46/171 Pages) STMICROELECTRONICS

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Interrupts

ST7DALIF2

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An external interrupt triggered on edge will be latched and the interrupt request

automatically cleared upon entering the interrupt service routine.

Caution:

The type of sensitivity defined in the External interrupt control register (EICR) applies to the

ei source. In case of a NANDed source (as described in Section 12: I/O ports), a low level

on an I/O pin configured as input with interrupt, masks the interrupt request even in case of

rising-edge sensitivity.

10.3

Peripheral interrupts

Different peripheral interrupt flags in the status register are able to cause an interrupt when

they are active if both:

●

The I bit of the CC register is cleared.

●

The corresponding enable bit is set in the control register.

If any of these two conditions is false, the interrupt is latched and thus remains pending.

Clearing an interrupt request is done by:

●

Writing “0” to the corresponding bit in the status register or

●

Access to the status register while the flag is set followed by a read or write of an

associated register.

Note:

The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being

enabled) will therefore be lost if the clear sequence is executed.

Figure 19.

Interrupt processing flowchart

I BIT SET?

IRET?

FROM RESET

LOAD PC FROM INTERRUPT VECTOR

STACK PC, X, A, CC

SET I BIT

FETCH NEXT INSTRUCTION

EXECUTE INSTRUCTION

THIS CLEARS I BIT BY DEFAULT

RESTORE PC, X, A, CC FROM STACK

INTERRUPT

PENDING?

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