HC705P6AGRSSLASHD datasheet(19/134 Pages) NXP

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General Release Specification

Functional Pin Description

MC68HC705P6A — Rev. 1.0

General Release Specification

General Description

1.4 Functional Pin Description

The following paragraphs describe the functionality of each pin on the

MC68HC705P6A package. Pins connected to subsystems described in

other chapters provide a reference to the chapter instead of a detailed

functional description.

1.4.1 V

and V

Power is supplied to the MCU through VDD and VSS. VDD is connected

to a regulated +5 volt supply and VSS is connected to ground.

Very fast signal transitions occur on the MCU pins. The short rise and

fall times place very high short-duration current demands on the power

supply. To prevent noise problems, take special care to provide good

power supply bypassing at the MCU. Use bypass capacitors with good

high-frequency characteristics and position them as close to the MCU as

possible. Bypassing requirements vary, depending on how heavily the

MCU pins are loaded.

1.4.2 OSC1 and OSC2

The OSC1 and OSC2 pins are the control connections for the on-chip

oscillator. The OSC1 and OSC2 pins can accept the following:

1. A crystal as shown in Figure 1-2(a)

2. A ceramic resonator as shown in Figure 1-2(a)

3. An external clock signal as shown in Figure 1-2(b)

The frequency, fosc, of the oscillator or external clock source is divided

by two to produce the internal bus clock operating frequency, fop. The

oscillator cannot be turned off by software unless the MOR bit, SWAIT,

is clear when a STOP instruction is executed.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705P6AGRS/D 数据表(PDF) 19 Page - NXP Semiconductors