HC705P6AGRSSLASHD datasheet(70/134 Pages) NXP

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Capture/Compare Timer

General Release Specification

MC68HC705P6A — Rev. 1.0

Capture/Compare Timer

8.4.2 Timer Status Register (TSR)

The timer status register, shown in Figure 8-3, contains flags to signal

the following conditions:

•

An active signal on the TCAP pin, transferring the contents of the

timer registers to the input capture registers

•

A match between the 16-bit counter and the output compare

registers, transferring the OLVL bit to the TCMP pin

•

A timer roll over from $FFFF to $0000

ICF — Input Capture Flag

The ICF bit is set automatically when an edge of the selected polarity

occurs on the TCAP pin. Clear the ICF bit by reading the timer status

input capture registers. Resets have no effect on ICF.

OCF — Output Compare Flag

The OCF bit is set automatically when the value of the timer registers

matches the contents of the output compare registers. Clear the OCF

bit by reading the timer status register with OCF set and then reading

the low byte ($0017) of the output compare registers. Resets have no

effect on OCF.

TOF — Timer Overflow Flag

The TOF bit is set automatically when the 16-bit counter rolls over

from $FFFF to $0000. Clear the TOF bit by reading the timer status

timer registers. Resets have no effect on TOF.

$0013

Bit 7

654321

Bit 0

Read:

ICF

OCF

TOF

00000

Reset:

00000

U = Undetermined

Figure 8-3. Timer Status Register (TSR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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