HC705P6AGRSSLASHD datasheet(40/134 Pages) NXP

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Resets

General Release Specification

MC68HC705P6A — Rev. 1.0

Resets

4.3 External Reset (RESET)

The RESET input is the only external reset and is connected to an

internal Schmitt trigger. The external reset occurs whenever the RESET

input is driven below the lower threshold and remains in reset until the

RESET pin rises above the upper threshold. The upper and lower

thresholds are given in Section 14. Electrical Specifications.

4.4 Internal Resets

The two internally generated resets are the initial power-on reset (POR)

function and the COP watchdog timer function.

4.4.1 Power-On Reset (POR)

The internal POR is generated at power-up to allow the clock oscillator

to stabilize. The POR is strictly for power turn-on conditions and should

not be used to detect a drop in the power supply voltage. There is a 4064

internal clock cycle oscillator stabilization delay after the oscillator

becomes active.

The POR will generate the RST signal and reset the MCU. If any other

reset function is active at the end of this 4064 internal clock cycle delay,

the RST signal will remain active until the other reset condition(s) end.

4.4.2 Computer Operating Properly (COP) Reset

When the COP watchdog timer is enabled (COP bit in the MOR is set),

the internal COP reset is generated automatically by a timeout of the

COP watchdog timer. This timer is implemented with an 18-stage ripple

counter that provides a timeout period of 65.5 ms when a 4-MHz

oscillator is used. The COP watchdog counter is cleared by writing a

logical zero to bit zero at location $1FF0.

The COP watchdog timer can be disabled by clearing the COP bit in the

MOR or by applying 2 x VDD to the IRQ/VPP pin (for example, during

bootloader). When the IRQ/VPP pin is returned to its normal operating

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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