HC705P6AGRSSLASHD datasheet(44/134 Pages) NXP

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Interrupts

General Release Specification

MC68HC705P6A — Rev. 1.0

Interrupts

condition code register is clear) and the corresponding interrupt enable

bit is set, the processor proceeds with interrupt processing. Otherwise,

the next instruction is fetched and executed. The SWI is executed the

same as any other instruction, regardless of the I-bit state.

When an interrupt is to be processed, the CPU puts the register contents

on the stack, sets the I bit in the CCR, and fetches the address of the

corresponding interrupt service routine from the vector table at locations

$1FF8 through $1FFF. If more than one interrupt is pending when the

interrupt vector is fetched, the interrupt with the highest vector location

shown in Table 5-1 will be serviced first.

An RTI instruction is used to signify when the interrupt software service

routine is completed. The RTI instruction causes the CPU state to be

recovered from the stack and normal processing to resume at the next

instruction that was to be executed when the interrupt took place.

Figure 5-1 shows the sequence of events that occurs during interrupt

processing.

Table 5-1. Vector Addresses for Interrupts and Reset

Flag

Name

Interrupts

CPU

Interrupt

Vector

Address

N/A

Reset

RESET

$1FFE–$1FFF

N/A

Software

SWI

$1FFC–$1FFD

N/A

External Interrupt

IRQ

$1FFA-$1FFB

TSR

ICF

Timer Input Capture

TIMER

$1FF8–$1FF9

TSR

OCF

Timer Output Compare

TIMER

$1FF8–$1FF9

TSR

TOF

Timer Overﬂow

TIMER

$1FF8–$1FF9

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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