HC705P6AGRSSLASHD datasheet(22/134 Pages) NXP

22 / 134 page

General Description

General Release Specification

MC68HC705P6A — Rev. 1.0

General Description

1.4.7 PD5 and PD7/TCAP

These two I/O pins comprise port D and one of them is shared with the

16-bit timer subsystem. The state of PD5 is software programmable and

is configured as an input during power-on or reset. PD7 is always an

input. It may be read at any time, regardless of which mode of operation

the 16-bit timer is in. Refer to Section 6. Input/Output Ports and

Section 8. Capture/Compare Timer.

1.4.8 TCMP

This pin is the output from the 16-bit timer’s output compare function. It

is low after reset. Refer to Section 8. Capture/Compare Timer.

1.4.9 IRQ/VPP (Maskable Interrupt Request)

This input pin drives the asynchronous interrupt function of the MCU in

user mode and provides the VPP programming voltage in bootloader

mode. The MCU will complete the current instruction being executed

before it responds to the IRQ interrupt request. When the IRQ/VPP pin is

driven low, the event is latched internally to signify an interrupt has been

requested. When the MCU completes its current instruction, the interrupt

latch is tested. If the interrupt latch is set and the interrupt mask bit (I bit)

in the condition code register is clear, the MCU will begin the interrupt

sequence.

Depending on the MOR LEVEL bit, the IRQ/VPP pin will trigger an

interrupt on either a negative edge at the IRQ/VPP pin and/or while the

IRQ/VPP pin is held in the low state. In either case, the IRQ/VPP pin must

be held low for at least one tILIH time period. If the edge- and level-

sensitive mode is selected (LEVEL bit set), the IRQ/VPP input pin

requires an external resistor connected to VDD for wired-OR operation.

If the IRQ/VPP pin is not used, it must be tied to the VDD supply. The

IRQ/VPP pin input circuitry contains an internal Schmitt trigger to improve

noise immunity. Refer to Section 5. Interrupts.

NOTE:

If the voltage level applied to the IRQ/VPP pin exceeds VDD, it may affect

the MCU’s mode of operation. See Section 3. Operating Modes.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705P6AGRS/D 数据表(PDF) 22 Page - NXP Semiconductors

HC705P6AGRS/D 数据表(HTML) 22 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载