HC705P6AGRSSLASHD datasheet(21/134 Pages) NXP

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General Release Specification

Functional Pin Description

MC68HC705P6A — Rev. 1.0

General Release Specification

General Description

1.4.2.3 External Clock

An external clock from another CMOS-compatible device can be

connected to the OSC1 input, with the OSC2 input not connected, as

shown in Figure 1-2(b).

1.4.3 RESET

Driving this input low will reset the MCU to a known startup state. The

RESET pin contains an internal Schmitt trigger to improve its noise

immunity. Refer to Section 4. Resets.

1.4.4 PA0–PA7

These eight I/O pins comprise port A. The state of any pin is software

programmable and all port A lines are configured as inputs during

power-on or reset. Port A has mask-option register enabled interrupt

capability with internal pullup devices selectable for any pin. Refer to

Section 6. Input/Output Ports.

1.4.5 PB5/SDO, PB6/SDI, and PB7/SCK

These three I/O pins comprise port B and are shared with the SIOP

communications subsystem. The state of any pin is software

programmable, and all port B lines are configured as inputs during

power-on or reset. Refer to Section 6. Input/Output Ports and Section

7. Serial Input/Output Port.

1.4.6 PC0-PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0, and PC7/VREFH

These eight I/O pins comprise port C and are shared with the A/D

converter subsystem. The state of any pin is software programmable

and all port C lines are configured as inputs during power-on or reset.

Refer to Section 6. Input/Output Ports and Section 9. Analog

Subsystem.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705P6AGRS/D 数据表(PDF) 21 Page - NXP Semiconductors