HC705P6AGRSSLASHD datasheet(60/134 Pages) NXP

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Serial Input/Output Port

General Release Specification

MC68HC705P6A — Rev. 1.0

Serial Input/Output Port

7.3.2 Serial Data Input (SDI)

The SDI pin becomes an input as soon as the SIOP subsystem is

enabled. New data may be presented to the SDI pin on the falling edge

of SCK.However, valid data must be present at least 100 nanoseconds

before the rising edge of SCK and remain valid for 100 nanoseconds

after the rising edge of SCK. See Figure 7-2.

7.3.3 Serial Data Output (SDO)

The SDO pin becomes an output as soon as the SIOP subsystem is

enabled. Prior to enabling the SIOP, PB5 can be initialized to determine

the beginning state. While the SIOP is enabled, PB5 cannot be used as

a standard output since that pin is connected to the last stage of the

SIOP serial shift register. Mask option register bit LSBF permits data to

be transmitted in either the MSB first format or the LSB first format. Refer

to 11.3 Mask Option Register (MOR) $1EFF–$1F00 for MOR LSBF

programming information.

On the first falling edge of SCK, the first data bit will be shifted out to the

SDO pin. The remaining data bits will be shifted out to the SDO pin on

subsequent falling edges of SCK. The SDO pin will present valid data at

least 100 nanoseconds before the rising edge of the SCK and remain

valid for 100 nanoseconds after the rising edge of SCK. See Figure 7-2.

7.4 SIOP Registers

The SIOP is programmed and controlled by the SIOP control register

(SCR) located at address $000A, the SIOP status register (SSR) located

at address $000B, and the SIOP data register (SDR) located at address

$000C.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705P6AGRS/D 数据表(PDF) 60 Page - NXP Semiconductors