HC705P6AGRSSLASHD datasheet(59/134 Pages) NXP

59 / 134 page

General Release Specification

SIOP Signal Format

MC68HC705P6A — Rev. 1.0

General Release Specification

Serial Input/Output Port

7.3 SIOP Signal Format

The SIOP subsystem is software configurable for master or slave

operation. No external mode selection inputs are available (for instance,

slave select pin).

7.3.1 Serial Clock (SCK)

The state of the SCK output normally remains a logic one during idle

periods between data transfers. The first falling edge of SCK signals the

beginning of a data transfer. At this time, the first bit of received data may

be presented at the SDI pin and the first bit of transmitted data is

presented at the SDO pin (see Figure 7-2). Data is captured at the SDI

pin on the rising edge of SCK. The transfer is terminated upon the eighth

rising edge of SCK.

The master and slave modes of operation differ only by the sourcing of

SCK. In master mode, SCK is driven from an internal source within the

MCU. In slave mode, SCK is driven from a source external to the MCU.

The SCK frequency is dependent upon the SPR0 and SPR1 bits located

in the mask option register. Refer to 11.3 Mask Option Register (MOR)

$1EFF–$1F00 for a description of available SCK frequencies.

Figure 7-2. SIOP Timing Diagram

SCK

SDO

SDI

100 ns

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705P6AGRS/D 数据表(PDF) 59 Page - NXP Semiconductors

HC705P6AGRS/D 数据表(HTML) 59 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载