HC705P6AGRSSLASHD datasheet(35/134 Pages) NXP

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General Release Specification

Low-Power Modes

MC68HC705P6A — Rev. 1.0

General Release Specification

Operating Modes

halt mode exit circuitry testing the oscillator stabilization delay timer (a

feature of the stop mode), which has been free-running (a feature of the

wait mode).

3.5.2 WAIT Instruction

The WAIT instruction places the MCU in a low-power mode which

consumes more power than stop mode. In wait mode, the internal clock

is halted, suspending all processor and internal bus activity. Internal

timer clocks remain active, permitting interrupts to be generated from the

16-bit timer and reset to be generated from the COP watchdog timer.

Execution of the WAIT instruction automatically clears the I bit in the

condition code register, enabling the IRQ external interrupt. All other

registers, memory, and input/output lines remain in their previous state.

If the 16-bit timer interrupt is enabled, it will cause the processor to exit

wait mode and resume normal operation. The 16-bit timer may be used

to generate a periodic exit from wait mode. Wait mode may also be

exited when an IRQ external interrupt or RESET occurs.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705P6AGRS/D 数据表(PDF) 35 Page - NXP Semiconductors