HC705P6AGRSSLASHD datasheet(68/134 Pages) NXP

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Capture/Compare Timer

General Release Specification

MC68HC705P6A — Rev. 1.0

Capture/Compare Timer

8.4 Timer I/O Registers

The following I/O registers control and monitor timer operation:

•

Timer control register (TCR)

•

Timer status register (TSR)

•

Timer registers (TRH and TRL)

•

Alternate timer registers (ATRH and ATRL)

•

Input capture registers (ICRH and ICRL)

•

Output compare registers (OCRH and OCRL)

8.4.1 Timer Control Register (TCR)

The timer control register, shown in Figure 8-2, performs these

functions:

•

Enables input capture interrupts

•

Enables output compare interrupts

•

Enables timer overflow interrupts

•

Controls the active edge polarity of the TCAP signal

•

Controls the active level of the TCMP output

Figure 8-2. Timer Control Register (TCR)

ICIE — Input Capture Interrupt Enable

This read/write bit enables interrupts caused by an active signal on

the TCAP pin. Resets clear the ICIE bit.

1 = Input capture interrupts enabled

0 = Input capture interrupts disabled

$0012

Bit 7

654321

Bit 0

Read:

ICIE

OCIE

TOIE

000

IEDG

OLVL

Write:

Reset:

000000

= Unimplemented

U = Undetermined

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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