HC705P6AGRSSLASHD datasheet(61/134 Pages) NXP

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General Release Specification

SIOP Registers

MC68HC705P6A — Rev. 1.0

General Release Specification

Serial Input/Output Port

7.4.1 SIOP Control Register (SCR)

This register is located at address $000A and contains two bits.

Figure 7-3 shows the position of each bit in the register and indicates

the value of each bit after reset.

SPE — Serial Peripheral Enable

When set, the SPE bit enables the SIOP subsystem such that

SDO/PB5 is the serial data output, SDI/PB6 is the serial data input,

and SCK/PB7 is a serial clock input in the slave mode or a serial clock

output in the master mode. Port B DDR and data registers can be

manipulated as usual (except for PB5); however, these actions could

affect the transmitted or received data.

The SPE bit is readable at any time. However, writing to the SIOP

control register while a transmission is in progress will cause the SPIF

and DCOL bits in the SIOP status register (see below) to operate

incorrectly. Therefore, the SIOP control register should be written

once to enable the SIOP and then not written to until the SIOP is to

be disabled. Clearing the SPE bit while a transmission is in progress

will 1) abort the transmission, 2) reset the serial bit counter, and 3)

convert the port B/SIOP port to a general-purpose I/O port. Reset

clears the SPE bit.

MSTR — Master Mode Select

When set, the MSTR bit configures the serial I/O port for master

mode. A transfer is initiated by writing to the SDR. Also, the SCK pin

becomes an output providing a synchronous data clock dependent

upon the oscillator frequency. When the device is in slave mode, the

SDO and SDI pins do not change function. These pins behave exactly

the same in both the master and slave modes.

$000A

Bit 7

654321

Bit 0

Read:

SPE

MSTR

0000

Write:

Reset:

00000000

= Unimplemented

Figure 7-3. SIOP Control Register (SCR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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