HC705P6AGRSSLASHD datasheet(55/134 Pages) NXP

55 / 134 page

General Release Specification

I/O Port Programming

MC68HC705P6A — Rev. 1.0

General Release Specification

Input/Output Ports

NOTE:

To avoid generating a glitch on an I/O port pin, data should be written to

the I/O port data register before writing a logic one to the corresponding

data direction register.

At power-on or reset, all DDRs are cleared, which configures all port pins

as inputs. The DDRs are capable of being written to or read by the

processor. During the programmed output state, a read of the data

level on the I/O port pin.

Table 6-3. Port C I/O Functions

DDRC

I/O Pin Mode

Accesses to

DDRC @ $0006

Accesses to Data

Read/Write

Read

Write

IN, Hi-Z

DDRC0–DDRC7

I/O Pin

See Note

OUT

DDRC0–DDRC7

PC0–PC7

NOTE: Does not affect input, but stored to data register

Table 6-4. Port D I/O Functions

DDRD

I/O Pin Mode

Accesses to

DDRD @ $0007

Accesses to Data

Read/Write

Read

Write

IN, Hi-Z

DDRD5

I/O Pin

See Note 1

OUT

DDRD5

PD5

NOTES:

1. Does not affect input, but stored to data register

2. PD7 is input only

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705P6AGRS/D 数据表(PDF) 55 Page - NXP Semiconductors

HC705P6AGRS/D 数据表(HTML) 55 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载