HC705P6AGRSSLASHD datasheet(54/134 Pages) NXP

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Input/Output Ports

General Release Specification

MC68HC705P6A — Rev. 1.0

Input/Output Ports

6.7 I/O Port Programming

Each pin on port A through port D (except pin 7 of port D) can be

programmed as an input or an output under software control as shown

in Table 6-1, Table 6-2, Table 6-3, and Table 6-4. The direction of a pin

is determined by the state of its corresponding bit in the associated port

data direction register (DDR). A pin is configured as an output if its

corresponding DDR bit is set to a logic one. A pin is configured as an

input if its corresponding DDR bit is cleared to a logic zero.

Table 6-1. Port A I/O Functions

DDRA

I/O Pin Mode

Accesses to

DDRA @ $0004

Accesses to Data

Read/Write

Read

Write

IN, Hi-Z

DDRA0–DDRA7

I/O Pin

See Note

OUT

DDRA0–DDRA7

PA0–PA7

NOTE: Does not affect input, but stored to data register

Table 6-2. Port B I/O Functions

DDRB

I/O Pin Mode

Accesses to

DDRB @ $0005

Accesses to Data

Read/Write

Read

Write

IN, Hi-Z

DDRB5–DDRB7

I/O Pin

See Note

OUT

DDRB5–DDRB7

PB5–PB7

NOTE: Does not affect input, but stored to data register

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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