HC705P6AGRSSLASHD datasheet(67/134 Pages) NXP

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General Release Specification

Timer Operation

MC68HC705P6A — Rev. 1.0

General Release Specification

Capture/Compare Timer

Because the counter is 16 bits long and preceded by a fixed divide-by-4

prescaler, the counter rolls over every 262,144 internal clock cycles.

Timer resolution with a 4-MHz crystal is 2

µs.

8.3.1 Input Capture

The input capture function is a means to record the time at which an

external event occurs. When the input capture circuitry detects an active

edge on the TCAP pin, it latches the contents of the timer registers into

the input capture registers. The polarity of the active edge is

programmable.

Latching values into the input capture registers at successive edges of

the same polarity measures the period of the input signal on the TCAP

pin. Latching values into the input capture registers at successive edges

of opposite polarity measures the pulse width of the signal.

8.3.2 Output Compare

The output compare function is a means of generating an output signal

when the 16-bit counter reaches a selected value. Software writes the

selected value into the output compare registers. On every fourth

internal clock cycle the output compare circuitry compares the value of

the counter to the value written in the output compare registers. When a

match occurs, the timer transfers the programmable output level bit

(OLVL) from the timer control register to the TCMP pin.

The programmer can use the output compare register to measure time

periods, to generate timing delays, or to generate a pulse of specific

duration or a pulse train of specific frequency and duty cycle on the

TCMP pin.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705P6AGRS/D 数据表(PDF) 67 Page - NXP Semiconductors