HC705P6AGRSSLASHD datasheet(95/134 Pages) NXP

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MC68HC705P6A — Rev. 1.0

General Release Specification

CPU Core

General Release Specification — MC68HC705P6A

Section 12. CPU Core

12.1 Contents

12.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

12.3

Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

12.3.1

Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

12.3.2

Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

12.3.3

Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

12.3.4

Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

12.3.5

Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .98

12.2 Introduction

The MC68HC705P6A has an 8-K memory map. Therefore, it uses only

the lower 13 bits of the address bus. In the following discussion, the

upper three bits of the address bus can be ignored. Also, the STOP

instruction can be modified to place the MCU in either the normal stop

mode or the halt mode by means of a MOR bit. All other instructions and

registers behave as described in this section.

12.3 Registers

The MCU contains five registers which are hard-wired within the CPU

and are not part of the memory map. These five registers are shown in

Figure 12-1 and are described in the following paragraphs.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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