HC705P6AGRSSLASHD datasheet(81/134 Pages) NXP

81 / 134 page

General Release Specification

A/D Status and Control Register (ADSC)

MC68HC705P6A — Rev. 1.0

General Release Specification

Analog Subsystem

CH2–CH0 — Channel Select Bits

CH2, CH1, and CH0 form a 3-bit field which is used to select an input

to the A/D converter. Channels 0–3 correspond to port C input pins

PC6–PC3. Channels 4–6 are used for reference measurements.

Channel 7 is reserved. If a conversion is attempted with channel 7

selected, the result will be $00. Table 9-1 lists the inputs selected by

bits CH0-CH3.

If the ADON bit is set and an input from channels 0–4 is selected, the

corresponding port C pin’s DDR bit will be cleared (making that port

C pin an input). If the port C data register is read while the A/D is on

and one of the shared input channels is selected using bit CH0–CH2,

the corresponding port C pin will read as a logic zero. The remaining

port C pins will read normally. To digitally read a port C pin, the A/D

subsystem must be disabled (ADON = 0), or input channels 5–7 must

be selected.

Table 9-1. A/D Multiplexer Input

Channel Assignments

Channel

Signal

AD0 — Port C, Bit 6

AD1 — Port C, Bit 5

AD2 — Port C, Bit 4

AD3 — Port C, Bit 3

4VREFH — Port C, Bit 7

5(VREFH + VSS)/2

6VSS

Reserved for Factory Test

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705P6AGRS/D 数据表(PDF) 81 Page - NXP Semiconductors

HC705P6AGRS/D 数据表(HTML) 81 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载