HC705P6AGRSSLASHD datasheet(47/134 Pages) NXP

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General Release Specification

Interrupt Types

MC68HC705P6A — Rev. 1.0

General Release Specification

Interrupts

IRQ interrupt. If the LEVEL bit in the mask option register is clear (edge-

sensitive only), the output of the internal edge detector flip-flop is

sampled and the input level on the IRQ/VPP pin is ignored. The interrupt

service routine address is specified by the contents of memory locations

$1FFA and $1FFB. If the port A interrupts are enabled by the MOR, they

generate external interrupts identically to the IRQ/Vpp pin.

NOTE:

The internal interrupt latch is cleared nine internal clock cycles after the

interrupt is recognized (immediately after location $1FFA is read).

Therefore, another external interrupt pulse could be latched during the

IRQ service routine.

Another interrupt will be serviced if the IRQ pin is still in a low state when

the RTI in the service routine is executed.

5.3.3.2 Input Capture Interrupt

The input capture interrupt is generated by the 16-bit timer as described

in Section 8. Capture/Compare Timer. The input capture interrupt flag

is located in register TSR and its corresponding enable bit can be found

in register TCR. The I bit in the CCR must be clear for the input capture

interrupt to be enabled. The interrupt service routine address is specified

by the contents of memory locations $1FF8 and $1FF9.

5.3.3.3 Output Compare Interrupt

The output compare interrupt is generated by a 16-bit timer as described

in Section 8. Capture/Compare Timer. The output compare interrupt

flag is located in register TSR and its corresponding enable bit can be

found in register TCR. The I bit in the CCR must be clear for the output

compare interrupt to be enabled. The interrupt service routine address

is specified by the contents of memory locations $1FF8 and $1FF9.

5.3.3.4 Timer Overflow Interrupt

The timer overflow interrupt is generated by the 16-bit timer as described

in Section 8. Capture/Compare Timer. The timer overflow interrupt flag

is located in register TSR and its corresponding enable bit can be found

in register TCR. The I bit in the CCR must be clear for the timer overflow

Freescale Semiconductor, Inc.

For More Information On This Product,

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