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HC705P6AGRS/D 数据表(PDF) 63 Page - NXP Semiconductors |
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HC705P6AGRS/D 数据表(HTML) 63 Page - NXP Semiconductors |
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63 / 134 page ![]() General Release Specification SIOP Registers MC68HC705P6A — Rev. 1.0 General Release Specification Serial Input/Output Port 7.4.3 SIOP Data Register (SDR) This register is located at address $000C and serves as both the transmit and receive data register. Writing to this register will initiate a message transmission if the SIOP is in master mode. The SIOP subsystem is not double buffered and any write to this register will destroy the previous contents. The SDR can be read at any time; however, if a transfer is in progress, the results may be ambiguous and the DCOL bit will be set. Writing to the SDR while a transfer is in progress can cause invalid data to be transmitted and/or received. Figure 7-5 shows the position of each bit in the register. This register is not affected by reset. $000C Bit 7 654321 Bit 0 Read: SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Write: Reset: Unaffected by reset Figure 7-5. Serial Port Data Register (SDR) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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