HC705P6AGRSSLASHD datasheet(46/134 Pages) NXP

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Interrupts

General Release Specification

MC68HC705P6A — Rev. 1.0

Interrupts

5.3 Interrupt Types

The interrupts fall into three categories: reset, software, and hardware.

5.3.1 Reset Interrupt Sequence

The RESET function is not in the strictest sense an interrupt; however,

it is acted upon in a similar manner as shown in Figure 5-1. A low-level

input on the RESET pin or internally generated RST signal causes the

program to vector to its starting address which is specified by the

contents of memory locations $1FFE and $1FFF. The I bit in the

condition code register is also set. The MCU is configured to a known

state during this type of reset as previously described in Section 4.

Resets.

5.3.2 Software Interrupt (SWI)

The SWI is an executable instruction. It is also a non-maskable interrupt

since it is executed regardless of the state of the I bit in the CCR. As with

any instruction, interrupts pending during the previous instruction will be

serviced before the SWI opcode is fetched. The interrupt service routine

address for the SWI instruction is specified by the contents of memory

locations $1FFC and $1FFD.

5.3.3 Hardware Interrupts

All hardware interrupts are maskable by the I bit in the CCR. If the I bit

is set, all hardware interrupts (internal and external) are disabled.

Clearing the I bit enables the hardware interrupts. Four hardware

interrupts are explained in the following subsections.

5.3.3.1 External Interrupt (IRQ)

The IRQ/VPP pin drives an asynchronous interrupt to the CPU. An edge

detector flip-flop is latched on the falling edge of IRQ/VPP. If either the

output from the internal edge detector flip-flop or the level on the

IRQ/VPP pin is low, a request is synchronized to the CPU to generate the

Freescale Semiconductor, Inc.

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