HC705P6AGRSSLASHD datasheet(65/134 Pages) NXP

65 / 134 page

MC68HC705P6A — Rev. 1.0

General Release Specification

Capture/Compare Timer

General Release Specification — MC68HC705P6A

Section 8. Capture/Compare Timer

8.1 Contents

8.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

8.3

Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

8.3.1

Input Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

8.3.2

Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

8.4

Timer I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

8.4.1

Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . .68

8.4.2

Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . .70

8.4.3

Timer Registers (TRH and TRL) . . . . . . . . . . . . . . . . . . . . .71

8.4.4

Alternate Timer Registers (ATRH and ATRL) . . . . . . . . . . .72

8.4.5

Input Capture Registers (ICRH and ICRL) . . . . . . . . . . . . .73

8.4.6

Output Compare Registers (OCRH and OCRL) . . . . . . . . .74

8.5

Timer During Wait/Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . .75

8.6

Timer During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

8.2 Introduction

This section describes the operation of the 16-bit capture/compare timer.

Figure 8-1 shows the structure of the capture/compare subsystem.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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