HC705P6AGRSSLASHD datasheet(62/134 Pages) NXP

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Serial Input/Output Port

General Release Specification

MC68HC705P6A — Rev. 1.0

Serial Input/Output Port

The MSTR bit is readable and writeable at any time regardless of the

state of the SPE bit. Clearing the MSTR bit will abort any transfers that

may have been in progress. Reset clears the MSTR bit as well as the

SPE bit, disabling the SIOP subsystem.

7.4.2 SIOP Status Register (SSR)

This register is located at address $000B and contains two bits.

Figure 7-4 shows the position of each bit in the register and indicates

the value of each bit after reset.

SPIF — Serial Port Interface Flag

SPIF is a read-only status bit that is set on the last rising edge of SCK

and indicates that a data transfer has been completed. It has no effect

on any future data transfers and can be ignored. The SPIF bit is

cleared by reading the SSR followed by a read or write of the SDR. If

the SPIF is cleared before the last rising edge of SCK, it will be set

again on the last rising edge of SCK. Reset clears the SPIF bit.

DCOL — Data Collision

DCOL is a read-only status bit which indicates that an illegal access

of the SDR has occurred. The DCOL bit will be set when reading or

writing the SDR after the first falling edge of SCK and before SPIF is

set. Reading or writing the SDR during this time will result in invalid

data being transmitted or received.

The DCOL bit is cleared by reading the SSR (when the SPIF bit is set)

followed by a read or write of the SDR. If the last part of the clearing

sequence is done after another transfer has started, the DCOL bit will

be set again. Reset clears the DCOL bit.

$000B

Bit 7

654321

Bit 0

Read:

SPIF

DCOL

000000

Write:

Reset:

00000000

= Unimplemented

Figure 7-4. SIOP Status Register (SSR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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