HC705P6AGRSSLASHD datasheet(58/134 Pages) NXP

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Serial Input/Output Port

General Release Specification

MC68HC705P6A — Rev. 1.0

Serial Input/Output Port

7.2 Introduction

The simple synchronous serial I/O port (SIOP) subsystem is designed to

provide efficient serial communications between peripheral devices or

other MCUs. The SIOP is implemented as a 3-wire master/slave system

with serial clock (SCK), serial data input (SDI), and serial data output

(SDO). A block diagram of the SIOP is shown in Figure 7-1. A mask

programmable option determines whether the SIOP is MSB or LSB first.

The SIOP subsystem shares its input/output pins with port B. When the

SIOP is enabled (SPE bit set in register SCR), port B DDR and data

registers are modified by the SIOP. Although port B DDR and data

registers can be altered by application software, these actions could

affect the transmitted or received data.

Figure 7-1. SIOP Block Diagram

8-BIT

SHIFT

STATUS

BAUD

RATE

CONTROL

GENERATOR

HCO5 INTERNAL BUS

INTERNAL

CPU CLOCK

SCK

SDI

SDO

76 54 32 10

765 43 21 0

76 54 32 10

I/O

$0B

$0C

$0A

CONTROL

LOGIC

SPE

SDI/PB6

SCK/PB7

SDO/PB5

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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