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HC705P6AGRS/D 数据表(PDF) 53 Page - NXP Semiconductors |
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HC705P6AGRS/D 数据表(HTML) 53 Page - NXP Semiconductors |
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53 / 134 page  General Release Specification Port D MC68HC705P6A — Rev. 1.0 General Release Specification Input/Output Ports 6.6 Port D Port D is a 2-bit port with one bidirectional pin (PD5) and one input-only pin (PD7). Pin PD7 is shared with the 16-bit timer. The port D data register is located at address $0003 and its data direction register (DDR) is located at address $0007. The contents of the port D data register are indeterminate at initial powerup and must be initialized by user software. Reset does not affect the data registers, but clears the DDRs, thereby setting PD5 to input mode. Writing a one to DDR bit 5 sets PD5 to output mode (see Figure 6-4). Port D may be used for general I/O applications regardless of the state of the 16-bit timer. Since PD7 is an input-only line, its state can be read from the port D data register at any time. Figure 6-4. Port D I/O Circuitry READ $0003 WRITE $0003 READ $0007 DATA REGISTER BIT I/O PIN OUTPUT INTERNAL HC05 DATA BUS RESET (RST) WRITE $0007 DATA DIRECTION REGISTER BIT Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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