DSP56303 datasheet(104/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

6-4

Freescale Semiconductor

Host Interface (HI08)

6.3 Overview

The HI08 is partitioned into two register banks, as Figure 6-1 shows. The host-side register bank

is accessible only to the host, and the DSP-side register bank is accessible only to the DSP core.

For the host, the HI08 appears as eight byte-wide locations mapped in its external address space.

The DSP-side registers appear to the DSP core as six 24-bit registers mapped into internal I/O X

memory space and therefore accessible via standard DSP56300 instructions and addressing

modes.

Figure 6-1. HI08 Block Diagram

TXL

TXM

TXH

HPCR

Latch

RXL

IVR

CVR

ICR

HDDR

HCR

HSR

HDR

DSP Peripheral Data Bus

HOST Bus

RXM

HBAR

ISR

HRX

HTX

Core DMA Data Bus

RXH

HCR = Host Control Register

HSR = Host Status Register

HPCR = Host Port Control Register

HBAR = Host Base Address Register

HTX = Host Transmit Register

HRX = Host Receive Register

HDDR = Host Data Direction Register

HDR = Host Data Register

ICR = Interface Control Register

CVR = Command Vector Register

IVR = Interrupt Vector Register

RXH = Receive Register High

RXM = Receive Register Middle

RXL = Receive Register Low

TXH = Transmit Register High

TXM = Transmit Register Middle

TXL = Transmit Register Low

Address

Comparator

ISR = Interface Status Register

Host-Side Registers

DSP-Side Registers

Control Registers

Data Registers

Control Registers

Data Registers

DSP

Side

Host

Side

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