DSP56303 datasheet(107/292 Pages) FREESCALE

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Operation

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

6-7

Host command

Transmit data register empty

Receive data register full

These interrupts are maskable via the Host Receive Interrupt Enable bit (HCR[0] = HRIE), the

Host Transmit Interrupt Enable bit (HCR[1] = HTIE), and the Host Command Interrupt Enable

bit (HCR[2] = HCIE), respectively. Receive Data Full and Transmit Data Empty interrupts move

data to/from the HTX and HRX data registers. The DSP interrupt service routine must read or

write the appropriate HI08 data register (HRX or HTX) to clear the interrupt condition.

Host commands allow the host to issue command requests to the DSP by selecting any of 128

DSP interrupt routines for execution. For example, the host may issue a command via the HI08

that sets up and enables a DMA transfer. The DSP56303 processor has reserved interrupt vector

addresses for application-specific service routines. However, this flexibility is independent of the

data transfer mechanisms in the HI08 and allows the host to force execution of any interrupt

handler (for example, SSI, SCI, IRQx, and so on).

To enable Host Command interrupts, the HCR[2] = HCIE bit is set on the DSP side. The host

then uses the Command Vector Register (CVR) to start an interrupt routine. The host sets the

Host Command bit (CVR[7] = HC) to request the command interrupt and the seven Host Vector

bits CVR[6–0] = HV[6–0] to select the interrupt address to be used. When the DSP core

recognizes the host command interrupt, the address of the interrupt taken is 2xHV. For host

command interrupts, the interrupt acknowledge from the DSP56303 program controller clears the

pending interrupt condition.

Figure 6-2. HI08 Core Interrupt Operation

X:HCR

X:HSR

Enable

HF3

HF2

HCIE HTIE HRIE HCR

HF1

HF0

HCP HTDE HRDF HSR

Status

DSP Core Interrupts

Receive Data Full

Transmit Data Empty

Host Command

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