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TNETA1570 数据表(PDF) 17 Page - Texas Instruments |
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TNETA1570 数据表(HTML) 17 Page - Texas Instruments |
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17 / 68 page  TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64BIT PCIHOST INTERFACE SDNS033B − JUNE 1995 − REVISED MAY 1996 17 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 timing requirements (see Figure 8) NO. MIN MAX UNIT 1 tsu(PIDSEL) Setup time, PIDSEL high before PCLK ↑ 7 ns 2 tsu(PAD) Setup time, PAD31 − PAD0 valid before PCLK ↑ 7 ns 3 tsu(PFRAME) Setup time, PFRAME low before PCLK ↑ 7 ns 4 tsu(PIRDY) Setup time, PIRDY low before PCLK ↑ 7 ns 5 th(PIDSEL) Hold time, PIDSEL high after PCLK ↑ 1 ns 6 th(PIRDY) Hold time, PIRDY low after PCLK ↑ 1 ns operating characteristics (see Figure 8) NO. MIN MAX UNIT 7 td(PTRDY) Delay time, PCLK ↑ to PTRDY↓ 2 11 ns PCLK (input) PFRAME (input) PCBE3− PCBE0 (input) PIRDY (input) PTRDY (output) PDEVSEL (output) Data Bus Cmd BE PIDSEL (input) 1 5 PAD31− PAD0 (I/O) Address Address Phase 2 3 4 7 6 Figure 8. TNETA1570 Write Operation (PCI SAR as Slave) |
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