TNETA1570 datasheet(4/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Terminal Functions (Continued)

PCI-bus interface (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

PIDSEL

131

PCI initialization and device select. PIDSEL is used as a chip select during configuration read

and write transactions.

PINTA

112

(open

drain)

PCI interrupt. PINTA is an interrupt request from PCI SAR.

PIRDY

147

I/O

(3 state)

PCI initiator ready. PIRDY indicates the initiating agent’s (bus master) ability to complete the

current data phase of the transaction. During a write, PIRDY indicates valid data on

PAD31 − PAD0. During a read, PIRDY indicates the master is prepared to accept the data.

PIRDY is used with PTRDY when wait cycles are inserted until both are asserted.

PPAR

155

I/O

PCI parity. PPAR is even parity across PAD31 − PAD0 and PCBE3 − PCBE0. For data phases,

PPAR is valid one clock after either PIRDY is asserted on a write or PTRDY is asserted on a read.

Once asserted, PPAR remains valid until one clock after the completion of the current data

PPAR

155

I/O

(3 state)

Once asserted, PPAR remains valid until one clock after the completion of the current data

phase. The master drives the PPAR for address- and write-data phases, and the target drives

PPAR for the read-data phase.

PPAR64

190

I/O

(3 state)

PCI parity. PPAR64 is even parity across AD63 − AD32 and CBE7 − CBE4. For data phases,

PPAR64 is valid one clock after either PIRDY is asserted on a write or PTRDY is asserted on

a read. Once asserted, PPAR64 remains valid until one clock after the completion of the current

data phase. The master drives the PPAR 64 for address and write-data phase, and the target

drives the PPAR for read-data phases.

PPERR

152

I/O

(3 state)

PCI parity error. PPERR reports a data-parity error on all commands except special cycle. An

agent cannot report a PPERR until it has claimed the access by PDEVSEL and completed a data

phase.

PREQ

118

PCI request. PREQ indicates to the arbiter that this agent desires use of the bus. Every master

has its own PREQ.

PREQ64

183

I/O

(3 state)

PCI request 64-bit transfer. PREQ64 is driven by the current master indicating the desire for a

64-bit access. When initiating a 64-bit transaction, the assertion of PREQ64 is coincident with

the assertion of PFRAME. If a 64-bit access is not acknowledged by PFRAME, the access

defaults to 32 bit. The transfer type (32 or 64 bit) is dynamically negotiated for each transaction

and remains constant for the length of the transaction.

PRST

113

PCI reset. PRST forces the PCI sequence of each device to a known state.

PSB1 − PSB0

110 − 111

PCI sideband. PSB1 − PSB0 lines define the size of the transfer when the TNETA1570 is the bus

master. The definitions of these signals are as follows:

00: 4-byte transfer

01: 16-byte transfer (except for receive-completion ring)

10: Payload transfer

11: Transfer to receive-completion ring (16-byte transfer)

PSB1 − PSB0 are synchronous to the address phase of the bus-master operations by the

TNETA1570. The sideband signals do not change upon a bus retry after disconnect.

PSERR

154

I/O

(open

drain)

PCI system error. PSERR reports address-parity errors and data-parity errors on special-cycle

commands.

PSTOP

150

I/O

(3 state)

PCI stop. PSTOP indicates that the current target is requesting the master to stop the current

transaction.

PTRDY

148

I/O

(3 state)

PCI target ready. PTRDY indicates the target agent’s (selected device) ability to complete the

current data phase of the transaction. During a read, PTRDY indicates that valid data is present

on PAD31 −PAD 0. During a write, PTRDY indicates that the target is prepared to accept data.

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