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TNETA1570 数据表(PDF) 11 Page - Texas Instruments

部件名 TNETA1570
功能描述  ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE
PDF  68 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETA1570 数据表(HTML) 11 Page - Texas Instruments

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TNETA1570
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH INTEGRATED 64BIT PCIHOST INTERFACE
SDNS033B − JUNE 1995 − REVISED MAY 1996
11
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
timing requirements (see Note 5 and Figure 2)
NO.
MIN
MAX
UNIT
1
tw(SEGCLKH)
Pulse duration, SEGCLK high
12
ns
2
tw(SEGCLKL)
Pulse duration, SEGCLK low
12
ns
3
tsu(SEGEN)
Setup time, SEGEN low before SEGCLK
↑
10
ns
4
th(SEGEN)
Hold time, SEGEN low after SEGCLK
↑
1
ns
NOTE 5: All output signals are generated on the rising edge of SEGCLK. All inputs are sampled on the rising edge of SEGCLK.
operating characteristics (see Note 5 and Figure 2)
NO.
MIN
MAX
UNIT
5
td(SEGCLAV)
Delay time, SEGCLK
↑ to SEGCLAV↓
1
20
ns
6
td(SEGSOC)
Delay time, SEGCLK
↑ to SEGSOC↑
1
20
ns
7
td(SEGDATA)
Delay time, SEGCLK
↑ to SEGDATA7−SEGDATA0 valid
1
20
ns
8
td(SEGPAR)
Delay time, SEGCLK
↑ to SEGPAR valid
1
20
ns
NOTE 5: All output signals are generated on the rising edge of SEGCLK. All inputs are sampled on the rising edge of SEGCLK.
SEGDATA7 −
SEGDATA0
(output)
SEGCLAV
(output)
SEGCLK
(input)
1
2
SEGSOC
(output)
6
7
SEGEN
(input)
Byte 1
Byte 2
Byte 3
Byte 49
Input
Ignored
Byte 50
Byte 48
Byte 51
4
5
3
SEGPAR
(output)
8
Figure 2. Segmentation-Cell Interface (PHY/ATM Low)



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