TNETA1570 datasheet(27/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

segmentation operation (continued)

The host interface on the TNETA1570 is a PCI interface with a selectable 64-bit or 32-bit address/data bus. The

boundaries of the data structures contained in host memory must be set to either 64 or 32 bits, depending upon

the configuration selected. The control-memory interface is a 32-bit interface and all data structures in control

memory contain 32-bit entries. The host interface on the TNETA1570 is responsible for ensuring the proper data

formatting within the limitations set for transactions between host memory and control memory and for host

accesses of internal registers.

scheduler table

Addressing

Control-memory address 00000 − 00CF7. An autonomous counter points to the

entries sequentially, thereby initiating the segmentation engine.

Addressing

Control-memory address 00000 − 00CF7. An autonomous counter points to the

entries sequentially, thereby initiating the segmentation engine.

Size

Max logical entries: 6200

Max 32-bit words:

3100

Min logical entries: 2

Min 32-bit words:

The scheduler table is located in control memory. It contains the order in which the transmit DMA channels are

serviced. This structure consists of 3100 32-bit words with two 16-bit entries per word, providing for a maximum

of 6200 entries. Only ten of the 16 bits in each entry are used, allowing for the simultaneous segmentation of

1023 packets. A zero entry means that no cell is transmitted during this cell opportunity. If a zero is detected,

the entry is skipped and the next entry is examined immediately. The scheduler table is initialized by the host

at startup.

ENTRY

DESCRIPTION

Word 0

Reserved (bits 31 − 26)

Entry 1 (bits 25 − 16)

Reserved (bits 15 − 10)

Entry 0 (bits 9 − 0)

Word N

Reserved (bits 31 − 26)

Entry 2N + I (bits 25 − 16)

Reserved (bits 15 − 10)

Entry 2N (bits 9 − 0)

Word 3099

Reserved (bits 31 − 26)

Entry 6199 (bits 25 − 16)

Reserved (bits 15 − 10)

Entry 6198 (bits 9 − 0)

NOTE: This table may be modified dynamically. This means that during normal operation of the device, the host

may modify the contents of the table while the transmit section of the device is operational. The ability

to dynamically modify the contents of the scheduler table must be comprehended in the design.

The MSBs for the table entries are bits 25 and 9 , the LSBs for the table entries are bits 16 and 0. Allowed values

in the entry fields are 0 to 1023. The address to the TX DMA state-table-entry word 0 can be found by using

the following formula:

(index value)

× 8 entries × 4 bytes per entry + 8000h

transmit DMA state table

Addressing

Control-memory address 0201h − 3FFFh (normal memory map). The entries are

addressed using the scheduler-table-entry values.

Addressing

Control-memory address 0201h − 3FFFh (normal memory map). The entries are

addressed using the scheduler-table-entry values.

Size

Max logical entries: 1023

Max 32-bit words:

8184

Min logical entries: 1

Min 32-bit words:

The transmit DMA state table resides in control memory and contains 1023 states, allowing for the simultaneous

segmentation of 1023 packets. Each state entry contains eight 32-bit words. The transmit DMA state table has

several entries that must be initialized, including whether a particular state is on or off and the location of the

first data buffer for the first packet sent. Four of the eight words in the transmit DMA state table are copied from

the descriptor entry located at the start of each data buffer queued for segmentation.

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