TNETA1570 datasheet(33/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

buffer offset (bits 23 −16)

The buffer offset (number of bytes offset from beginning of the payload area) is a pointer into the buffer that

indicates to the segmentation unit where the real data begins. When a new buffer descriptor is imported by the

TNETA1570, the TNETA1570 stores it in TX DMA state table-entry memory. The segmentation unit must add

the buffer offset to the start address to create the initial current-buffer-data address. An offset of 0 means that

the data starts immediately.

buffer-data-byte count (bits 15 −0)

This field is set by the host to indicate the number of bytes in the buffer that are to be segmented. The maximum

buffer size is 64K bytes, allowing an entire packet to be placed in a single buffer. Minimum size is one byte.

word 1

Start-of-Next-Buffer Pointer (bits 29 − 0)

This word provides the upper 30 bits of the 32-bit address of the next data buffer in the buffer chain; the lower

two bits of the address are always set to zero. If the buffer being segmented is the last buffer in the chain, this

entry is not used by the TNETA1570. The data buffer (with descriptor entry) is aligned to either a 32-bit or 64-bit

boundary, depending on whether the 64-bit or 32-bit PCI-host interface is selected.

word 2

GFC (bits 31 − 28)

VPI (bits 27 − 20)

VCI (bits 19 − 4)

PTI (bits 3−1)

CLP (bit 0)

This word provides the 4-byte ATM header. The PTI field is changed in the last cell of the packet to indicate EOP

(i.e., PTI = 0

× 1). This word is only read into the TX DMA state table for the first buffer in a packet. For subsequent

buffers, this word is not copied. The AAL5 ANSI and ITU-T specifications require that the last cell in an AAL5

packet set the PTI field to xx1 to indicate EOP.

word 3

CPCS-UU (bits 31 − 24)

CPI (bits 23 − 16)

User defined (bits 15 − 0)

CPCS-UU (bits 31 −24), CPI (bits 23 −16)

This field is set by the host and copies directly into the control field of the outgoing AAL5 trailer. This field is only

copied over for the first buffer in a packet. For subsequent buffers, this field is ignored.

user defined (bits 15 −0)

This field is available for use by the user and is not used or modified by the TNETA1570.

transmit completion rings with/without interrupt

Addressing

In host memory. The entries are addressed using the TX completion-ring pointers.

Size: set in the TX

completion-ring-size

Max logical entries: 8192

Max 32-bit words: 8192

Size: set in the TX

completion-ring-size

registers

Max logical entries: 8192

Max 32-bit words: 8192

Min logical entries: 1

registers

Min logical entries: 1

Min 32-bit words: 1

The structure of the transmit completion rings with/without interrupt located in host memory follows. An entry

is posted to the completion ring when a buffer completes segmentation. The starting address of the buffer

completing segmentation is written into the transmit completion ring. When segmentation of a buffer is

completed and the transmit completion ring with interrupt has been selected and updated, an interrupt is

generated on either a buffer or packet basis, depending upon the state of the bit in the configuration register.

If the transmit completion ring without interrupt has been selected and updated, an interrupt is not generated.

TNETA1570 数据表(PDF) 33 Page - Texas Instruments

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