TNETA1570 datasheet(62/68 Pages) TI1

62 / 68 page

TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

interrupt-mask register

PCI Mask Bits (bits 31 − 16)

Reserved (bits 15 − 10)

Mask Bits (bits 9 − 0)

This register is used to mask interrupts caused by the conditions given in the status register. This register has

a bit-to-bit correspondence with the status register. This register is read/write and is accessed as a 32-bit word,

although not all 32 bits may be used. This register is cleared upon a hardware or software reset. When a bit in

the interrupt-mask register is set, an interrupt is generated if the corresponding bit in the status register is also

set.

reassembly-global-timer register

Reassembly-Global Timer (bits 15 − 0)

This register contains the value that is loaded into the reassembly-aging timer. When the reassembly-aging

counter expires, a reassembly time-out count in one of the RX DMA state table entries is incremented, if that

channel is currently receiving a packet. The entries in the RX DMA state table are serviced on a round-robin

basis. This register is a 16-bit register and is read/write. This register is cleared upon a hardware or software

reset.

RAT-cycle-count register

Reserved (bit 15 )

RAT_Cycle-Count_Register (bits 14 − 0)

This register is used in the reassembly-aging process. The value must be equal to or greater than the aging

opportunities in one trip through the VPI/VCI DMA pointer table. The minimum value entered in this field is

4096 + [the sum of all (valid VCI range) in the RX VPI/VCI DMA pointer table].

Example( decimal values):

Entry 0 has the valid VCI range = 255.

Entry 8 has the valid VCI range = 0.

Entry 1234 has the valid VCI range = 1234.

Entry 4095 has the valid VCI range = 5432.

All other entries are disabled.

The minimum value is 4096 + 255 + 0 + 1234 + 5432 = 11017. The maximum value is limited by the number

of bits available (15) for this field. This is a 16-bit register with read/write capability and is cleared upon a

hardware or software reset.

RX unknown register

Reserved (bits 31 − 29)

Control (bit 28)

VPI (bits 27−16)

VCI (bits 15 − 10)

This register contains the ATM header, including the VPI/VCI value of a received cell under the following

conditions:

D The cell VPI address entry in the RX VPI/VCI DMA pointer table is not enabled.

D The cell VCI address does not fall within the range of active values in the RX VPI/VCI DMA pointer table.

D The cell’s on bit and filter bit in the RX DMA state table is not set.

D The cell is an idle cell, i.e., a cell with the ATM header set to a binary value of xxxx 0000 0000 0000 0000

0000 0000 xxx1 (also known as an invalid cell).

TNETA1570 数据表(PDF) 62 Page - Texas Instruments

TNETA1570 数据表(HTML) 62 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

数据表下载