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TNETA1570 数据表(PDF) 63 Page - Texas Instruments |
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TNETA1570 数据表(HTML) 63 Page - Texas Instruments |
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63 / 68 page ![]() TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64BIT PCIHOST INTERFACE SDNS033B − JUNE 1995 − REVISED MAY 1996 63 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PRINCIPLES OF OPERATION RX unknown register (continued) This register holds the value first written into it until it has been read by the host. This is a 32-bit register, read only, and is cleared when a hardware or software reset occurs. The register is also cleared when it is read by the host. This register also contains a control bit that is set when a value is written into the register by the TNETA1570 and cleared when the register is read by the host. When a value is written to this register, a bit in the status register is set and an interrupt may or may not be generated, depending upon the state of the interrupt-mask bit in the interrupt-mask register. TX completion ring without interrupt (WOI)-size register Reserved (bits 15 − 13) TX Completion Ring WOI Size (bits 12 − 0) This register contains the size of the TX completion ring without interrupt. The maximum size of this ring is 8192 entries. The size is restricted to a power of 2, I.e., 2, 4, 8, 1 6, 32, 64, 1 28, etc. This field is coded (ring size −1) to account for entry 0; therefore, for a ring with 16 entries, the value of 00 0000 1111 is entered in this field. This is a 16-bit register, read/write, and is cleared when a hardware or software reset occurs. The value in the register is compared to an internal pointer counter that is incremented when a completion-ring entry is processed. When the value of the pointer counter equals the value in the register, the pointer value is reset and the next pointer value is zero. TX completion ring with interrupt (WI)-size register Reserved (bits 15 − 13) TX Completion Ring WI Size (bits 12 − 0) This register contains the size of the TX completion ring with interrupt. The maximum size of this ring is 8192 entries. The size is restricted to a power of 2, i.e., 2, 4, 8, 16, 32, 64, 128, etc. This field is coded (ring size −1) to account for entry 0; therefore, for a ring with 16 entries, the value of 00 0000 1111 is entered in this field. This is a 16-bit register, read/write, and is cleared when a hardware or software reset occurs. The value in the registers is compared to an internal pointer counter that is incremented when a completion-ring entry is processed. When the value of the pointer counter equals the value in the register, the pointer value is reset and the next pointer value is zero. RX completion ring without interrupt (WOI)-size register Reserved (bits 15 − 10) RX Completion Ring WOI Size (bits 9 − 0) This register contains the size of the RX completion ring without interrupt. The maximum size of this ring is 1024 entries. The size is restricted to be a power of 2, i.e., 2, 4, 8, 16, 32, 64, 128, etc. This field is coded (ring size −1) to account for entry 0; therefore, for a ring with 16 entries, the value of 00 0000 1111 is entered in this field. This is a 16-bit register, read/write, and is cleared when a hardware or software reset occurs. The value in the registers is compared to an internal pointer counter that gets incremented when a completion-ring entry is processed. When the value of the pointer counter equals the value in the register, the pointer value is reset and the next pointer value is zero. RX completion ring with interrupt (WI)-size register Reserved (bits 15 − 10) RX Completion Ring WI Size (bits 9 − 0) This register contains the size of the RX completion ring with interrupt. The maximum size of this ring is 1024 entries. The size is restricted to a power of 2, i.e., 2, 4, 8, 16, 32, 64, etc. This field is coded (ring size −1) to account for entry 0; therefore, for a ring with 16 entries, the value of 00 0000 1111 is entered in this field. This is a 16-bit register, read/write, and is cleared when a hardware or software reset occurs. |
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