TNETA1570 datasheet(57/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

UTOPIA-to-PCI data flow for reassembly unit

little-endian configuration (PCI compliant)

There are two scenarios for TNETA1570 cell-payload PCI writes to host memory when the TNETA1570 is

configured as a little-endian device. These are 32-bit PCI cell-payload writes and 64-bit PCI cell-payload writes.

32-bit PCI cell-payload writes

The following table shows the PCI-bus byte/address ordering when cell-payload bytes are input to the

reassembly UTOPIA port in the order 0, 1, 2, 3, 4, 5, . . .

The top-down order of the following chart represents the time order of 32-bit word writes by the TNETA1570.

PCI ADDRESS

PCI ADDRESS BITS

×10

×14

×18

64-bit PCI cell-payload writes

The following table shows the PCI-bus byte/address ordering when cell-payload bytes are input to the

reassembly UTOPIA port in the order 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, . . .

The top-down order of the following chart represents the time order of 64-bit word writes by the TNETA1570.

PCI ADDRESS

PCI ADDRESS BITS

×10

×18

×20

big-endian configuration

There are two scenarios are for TNETA1570 cell-payload PCI writes to host memory when the TNETA1570 is

configured as a big-endian device. These are 32-bit PCI cell-payload writes and 64-bit PCI cell-payload writes.

32-bit PCI cell-payload writes

The following table shows the PCI-bus byte/address ordering when cell-payload bytes are input to the

reassembly UTOPIA port in the order 0, 1, 2, 3, 4, 5, . . .

The top-down order of the following chart represents the time order of 32-bit word writes by the TNETA1570.

PCI ADDRESS

PCI ADDRESS BITS

×10

×14

×18

TNETA1570 数据表(PDF) 57 Page - Texas Instruments

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