TNETA1570 datasheet(37/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

entries of receive DMA state table

The definitions of the fields within each word entry are given below:

word 0

Config (bits 31 − 25)

Reserved (bits 24 − 22)

EFCN Cell Counter (bits 21 − 11)

Current-Packet Length (bits 10 − 0)

ACT (ACTive) (bit 31)

This bit is set by the TNETA1570 to indicate that this DMA channel is active and a packet reassembly is currently

underway. This bit is cleared by the TNETA1570 when the EOP bit is detected and the reassembly of a packet

is complete.

reserved (bit 30)

receive complete-interrupt posting (bit 29)

When this bit is set, the receive completion ring with interrupt is used for posting a completion notice when

reassembly of a packet is complete. When this bit is cleared, the receive completion ring without interrupt is

used. This bit must be initialized by the host.

wait for EOP (bit 28)

This bit is set by the TNETA1570 when either a packet time-out or packet overflow condition is detected. All

packet reassembly is then disabled until an EOP cell is detected. This bit also is set if a free buffer is not available

for reassembling an incoming packet. The TNETA1570 clears this bit when the cell containing the EOP

indication is received.

packet-type indicator (bits 27 and 26)

These bits are set by the host to indicate whether AAL5, PTI-based transparent-AAL, or counter-based

transparent-AAL processing is performed on the incoming packet. The following values are defined for these

bits:

BIT 27

BIT 26

INDICATION

PTI-based transparent-AAL packet

AAL5 packet

Counter-based transparent-AAL packet

Invalid

FIFO/free-buffer ring indicator (bit 25)

This bit is set by the host to indicate that the TNETA1570 uses the FIFO structure to fetch free buffers for this

receive channel. When this bit is cleared by the host, the TNETA1570 uses the free-buffer-ring structure to fetch

free buffers for this receive channel.

EFCN-cell counter (bits 21−11)

This field counts the number of cells that are received with the explicit forward congestion notification indicator

(EFCN) in the PTI bits set (i.e., the PTI field is set to 01x). This field is cleared after reassembly of a packet is

complete. This field is updated by the TNETA1570. The counter value is one greater than the actual value

(actual + l), if the TNETA1570 experiences buffer starvation and the last received cell has the EFCN flag set.

current-packet length (bits 10 −0)

This field counts the number of cells received on this DMA channel. If the value in this field exceeds 1366 cells

before an EOP cell is detected, a packet-overflow error occurs, bit 28 is set, and EOP processing is initiated.

This field is only valid for AAL5 packets.

TNETA1570 数据表(PDF) 37 Page - Texas Instruments

TNETA1570 数据表(HTML) 37 Page - Texas Instruments

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