TNETA1570 datasheet(47/68 Pages) TI1

47 / 68 page

TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

cell interface (continued)

When PHY/ATM is high (PHY mode), the cell-interface port configuration is defined as a PHY-RX port for the

segmentation unit and the cell-interface port configuration is a PHY-TX port for the reassembly unit. The clock

speed supported by the interface is up to 33 MHz nominal. The ATMCLK is connected in this mode and is

configured as an output that is always low.

When PHY/ATM is low (ATM mode), the cell-interface port configuration is defined as an ATM-TX port for the

segmentation unit and the cell-interface port configuration is an ATM-RX port for the reassembly unit. The

ATMCLK is used as the clock source to provide for data transfers/synchronization. The ATMCLK has is

connected to the SEGCLK and RESCLK in the ATM mode.

The interface is designed to work synchronously for an 8-bit data path. The interface uses either an octet-level

handshake or a cell-level handshake. The clock generated by the interface is 33 MHz nominal, using the PCI

clock.

segmentation-unit interface, PHY mode

The segmentation-unit interface on the TNETA1570 outputs RXDATA on the UTOPIA interface in PHY mode.

This cell interface works on the low-to-high transition of SEGCLK to sample and generate signals. All signals

are active high, unless denoted via a bar over the signal name.

SEGCLK

Clock (RXCLK) input. Data transfer/synchronization clock for synchronizing transfers on SEGDATA. When

operating in PHY mode, the SEGCLK is sourced from the UTOPIA interface.

SEGDATA (bits 7 −0)

Data (RXDATA) output. Byte-wide true data sourced by the TNETA1570. SEGDATA7 is the MSB.

SEGPAR

Parity (RXPRTY) output. SPAR is the odd-parity bit over SEGDATA.

SEGSOC

Start of cell (RXSOC) output. Active-high signal sourced by the TNETA1570 when SEGDATA contains the first

valid byte of the cell.

SEGEN

Enable (RXENB) input. This active-low signal is received by the TNETA1570 when a valid byte SEGDATA is

sent during the next clock cycle.

SEGCLAV

Empty/cell available (RXEMPTY/RXCLAV) output. An indication that a complete cell is available.

reassembly-unit interface, PHY mode

The reassembly unit interface on the TNETA1570 inputs TXDATA from the UTOPIA interface in PHY mode. This

receive cell interface works on the low-to-high transition of RESCLK to sample and generate signals. All signals

are active high unless denoted via a bar over the signal name.

RESCLK

Clock (TXCLK) input. Data transfer/synchronization clock for synchronizing transfers on RESDATA. When

operating in PHY mode, the RESCLK is sourced from the UTOPIA interface.

TNETA1570 数据表(PDF) 47 Page - Texas Instruments

TNETA1570 数据表(HTML) 47 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

数据表下载