TNETA1570 datasheet(49/68 Pages) TI1

49 / 68 page

TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

RESCLK

Clock (RXCLK) input. Data transfer/synchronization clock for synchronizing transfers on RESDATA. When

operating in ATM mode, the ATMCLK is used as the source for the RESCLK.

RESDATA

Data (RXDATA) input. RESDATA7 is the MSB.

RESPAR

Parity (RXPAR) input. RESPAR is the odd-parity bit over RESDATA.

RESSOC

Start of cell (RXSOC) input. This active-high signal is received by the TNETA1570 when RESDATA contains

the first valid byte of the cell.

RESEN

Empty/cell available (RXEMPTY/RXCLAV) input. An indication that there is no valid data to be transferred in

the current cycle. (Functional description does not match pin name for ATM mode).

RESCLAV

Enable (RXENB) output. This active-low signal is sent by the TNETA1570 when a valid byte of RESDATA is sent

during the next clock cycle. (Functional description does not match pin name for ATM mode).

RESPERR

Parity error output. (Not required by the UTOPIA specification) Active-low signal asserted by the reassembly

unit to indicate parity error was present at the previous rising RESCLK edge.

internal FIFOs

The TNETA1570 has a transmit FIFO for internal interfacing between the segmentation engine and the

cell-transmit block. The TX FIFO size is 32 (double words) x 64 (bits), which hold 4 cells. Likewise, the

TNETA1570 has a receive FIFO for internal interfacing between the reassembly engine and the cell-receive

block. The RX FIFO size is 64 (double words) x 64 (bits), which hold 8 cells.

host interface

The

TNETA1570

incorporates

PCI

local-bus

specification

revision

2.0

(April

30,

1993)

compliant-host-interface. The following sections describe the features and operation of the PCI-host interface.

host-interface overview

The TNETA1570 operates as a PCI-slave device for configuration cycles, accesses to internal registers, and

accesses to the onboard control memory. It also acts as a PCI-master device for accessing data structures that

are contained in host memory.

As a master, the TNETA1570 incorporates the following features:

D Directly supports the memory-read, memory-write, configuration-read and configuration-write PCI

commands and aliases the memory-read multiple, memory-read line, and memory write and invalidate to

the basic memory commands.

D Supports single data-cycle transfers and disconnects with retry after the first data cycle

D Responds to accesses as a 32-bit agent with medium PDEVSEL timing (single-wait state)

D Utilizes a 1-M block of addresses, which is mapped into the host-memory space using a single

base-address register

D Does not support resource locking

TNETA1570 数据表(PDF) 49 Page - Texas Instruments

TNETA1570 数据表(HTML) 49 Page - Texas Instruments

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