TNETA1570 datasheet(53/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

device command and status registers (continued)

The status register allows the host to monitor the condition of the peripheral device. The individual bits within

the status register are defined in the following table.

BIT

NAME

FUNCTION

RESET

VALUE

0− 6

Reserved

Always return 0

Fast back-to-back

enable

This bit indicates that the device is capable of performing fast back-to-back transactions. The

TNETA1570 does not support fast back-to-back transactions; therefore, this bit is hardwired

to 0.

Data parity reported

This bit is set by the PCI-master unit in the TNETA1570 when all of the following conditions are

met:

The TNETA1570 asserted PERR or observed PERR asserted.

The TNETA1570 PCI-master unit is the bus master during the observed PERR.

The parity-error-response bit (command-register bit 6) is set.

9,10

DEVSEL timing

This bit indicates the decode-response-time capability of the device. The TNETA1570 decode

logic supports medium DEVSEL timing; therefore, these bits are hardwired to 01.

Signaled target abort

This bit is set by the PCI-slave unit in the TNETA1570 to indicate that it has initiated a target abort.

Received-target abort

This bit is set by the PCI-master unit in the TNETA1570 to indicate that it has received a target

abort when acting as a bus master.

Initiated-master abort

This bit is set by the PCI-master unit in the TNETA1570 to indicate that It has initiated a master

abort.

Signaled system error

This bit is set by the TNETA1570 to indicate that it signaled a system error on SERR.

Detected parity error

This bit is set by the TNETA1570 to indicate that it detected a parity error, which was not

necessarily reported on PPERR if parity reporting is disabled.

cache-line-size register

This register enables the host to inform the device of the cache-line size for the usage of the write and invalidate

PCI command. The TNETA1570 does not support the write and Invalidate command as a master so this register

is not implemented and returns all zeroes when read.

latency-timer register

The latency-timer register is provided so that the host can restrict the continued usage of the PCI bus by a master

involved in a multiple data-cycle transaction after its PGNT has been removed. The host is required to write a

value into this register indicating the maximum number of PCI cycles that the master can hold the bus (beginning

from the assertion of PFRAME). If PGNT is never removed during the transaction, the value in the latency-timer

value is not used. Since the TNETA1570 supports transactions with multiple data cycles, the latency-timer

cleared on software reset.

built-in self-test (BIST) register

BIST is not supported by the TNETA1570. Reading this register returns all zeroes.

TNETA1570 数据表(PDF) 53 Page - Texas Instruments

TNETA1570 数据表(HTML) 53 Page - Texas Instruments

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