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TNETA1570 数据表(PDF) 26 Page - Texas Instruments |
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TNETA1570 数据表(HTML) 26 Page - Texas Instruments |
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26 / 68 page  TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64BIT PCIHOST INTERFACE SDNS033B − JUNE 1995 − REVISED MAY 1996 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PRINCIPLES OF OPERATION internal registers (continued) DESCRIPTION SIZE R/W Configuration register 32 bits R/W Configuration register Status register 32 bits 32 bits R/W R Status register Interrupt-mask register 32 bits 32 bits R R/W Interrupt-mask register Reassembly-global-timer register 32 bits 16 bits R/W R/W Reassembly-global-timer register Maximum RX DMA state-table register 16 bits 16 bits R/W R/W Maximum RX DMA state-table register RX unknown register 16 bits 32 bits R/W R RX unknown register TX completion ring with interrupt-size register TX completion ring without interrupt-size register 32 bits 16 bits 16 bits R R/W R/W TX completion ring with interrupt-size register TX completion ring without interrupt-size register RX completion ring with interrupt-size register 16 bits 16 bits 16 bits R/W R/W R/W TX completion ring without interrupt-size register RX completion ring with interrupt-size register RX completion ring without interrupt-size register 16 bits 16 bits 16 bits R/W R/W R/W RX completion ring with interrupt-size register RX completion ring without interrupt-size register TX packet-segmentation ring-size register 16 bits 16 bits 16 bits R/W R/W R/W RX completion ring without interrupt-size register TX packet-segmentation ring-size register FIFO free-buffer-size register 16 bits 16 bits 16 bits R/W R/W R/W FIFO free-buffer-size register HEC-error counter 16 bits 16 bits R/W R HEC-error counter Unknown-protocols counter 16 bits 32 bits R R Unknown-protocols counter AAL5 CPCS PDU-discard counter 32 bits 16 bits R R AAL5 CPCS PDU-discard counter ATM-cells-received counter 16 bits 32 bits R R ATM-cells-received counter ATM-cells-transmitted counter 32 bits 32 bits R R ATM-cells-transmitted counter VCI-mask register 32 bits 16 bits R R/W VCI-mask register FIFO maximum occupancy value 16 bits 16 bits R/W R FIFO maximum occupancy value Scheduler-table-size register 16 bits 16 bits R R/W Scheduler-table-size register Software reset 16 bits 32 bits R/W W Software reset TX completion ring without interrupt-pointer address 32 bits 32 bits W R/W TX completion ring without interrupt-pointer address TX completion ring with interrupt-pointer address 32 bits 32 bits R/W R/W TX completion ring with interrupt-pointer address RX completion ring without interrupt-pointer address 32 bits 32 bits R/W R/W RX completion ring without interrupt-pointer address RX completion ring with interrupt-pointer address 32 bits 32 bits R/W R/W host interface The TNETA1570 incorporates a PCI revision 2.0 (April 30, 1993) compliant host interface. The TNETA1570 operates as a 32-bit PCI-slave device for configuration cycles, accesses to internal registers, and accesses to the onboard control memory. It also acts as a PCI-master device for accessing data structures that are contained in host memory. The TNETA1570 initiates 64-bit or 32-bit data transfers to and from data structures in host memory, but only initiates 32-bit data transfers to and from control structures in host memory. segmentation operation The transmit operation of the TNETA1570 utilizes data structures in both host memory and control memory. The packets being segmented are stored in buffers in host memory, along with the descriptor-entry information for that buffer. The transmit completion rings and packet-segmentation rings also are located in host memory. Control memory contains the scheduler table and the TX DMA state table. These data structures are described in the following paragraphs. The segmentation process for the TNETA1570 is based on the segmentation of buffers instead of the segmentation of packets. EOP processing still is required to add the AAL5 trailer to the last cell in an AAL5 packet. However, segmentation can start once a buffer ending on an even 48-byte boundary is filled, instead of waiting until all of a packet is stored in memory. The segmentation process also uses link entries to queue up buffers associated with the same packet for segmentation. For the targeted application, link entries provide a more efficient use of host memory for storing descriptor and user data. The packet provides a more efficient use of host memory for storing descriptor and user data. The packet-segmentation rings are used to queue up different packets for segmentation. |
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