TNETA1570 datasheet(65/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

TX FIFO maximum occupancy value (bits 11 −8), and RX FIFO maximum occupancy value (bits 4 −0)

These registers contain the maximum occupancy value for the TX and RX FIFOs experienced during operation.

An internal register keeps the current occupancy value of the FIFOs. If the value in the internal register is greater

than the value in the register for more than one consecutive cycle, the value is written into the register. The

values in the registers are used to measure the usage of the internal FIFOs to optimize a future revision of the

TNETA1570. The reset value is zero.

scheduler-table-size register

Reserved (bits 31 − 16)

Reserved (bits 15 − 12)

Scheduler-Table-Size Register (bits 11 − 0)

This register contains the size (in 32-bit words) of the scheduler table. It is initialized by the host. Maximum value

is 3100(dec), Minimum value is one. The reset value is zero. This register is programmed before the EN_TX

is set.

software reset

Reserved (bits 31 − 0)

A write to this address location forces the TNETA1570 into reset. The address is decoded and an internal reset

pulse with sufficient length is generated. The duration of reset is max ten clock cycles.

completion-ring address registers

TX completion ring WOI address (bits 31 − 0)

TX completion ring WI address (bits 31 − 0)

RX completion ring WOI address (bits 31 − 0)

RX completion ring WI address (bits 31 − 0)

The completion-ring address registers hold the addresses to the completion rings in host memory. The value

is set by the host. The address is aligned to the size of the ring to ensure that the first entry is always on an even

2^n address boundary.

counters

HEC-error counter

This 16-bit counter counts the number of cells dropped due to HEC errors. This rollover counter causes a bit

in the status register to be set on rollover. This counter is read only and is cleared when a hardware or software

reset occurs. This counter does not clear on a read by the host.

unknown-protocols counter

This 32-bit counter counts the number of cells whose header is posted in the RX unknown register. This rollover

counter causes a bit in the status register to be set on rollover. This counter is read only and is cleared when

a hardware or software reset occurs. This counter does not clear on a read by the host.

AAL5 CPCS PDU-discard counter

This 16-bit counter counts the number of receive-AAL5 packets that were discarded because no receive free

buffers are available. This rollover counter causes a bit in the status register to be set on rollover. This counter

is read only and is cleared when a hardware or software reset occurs. This counter does not clear on a read

by the host.

TNETA1570 数据表(PDF) 65 Page - Texas Instruments

TNETA1570 数据表(HTML) 65 Page - Texas Instruments

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